1. Field of the Invention
The present invention relates to a memory integrated circuit and methods for manufacturing the same, and more particularly, to a memory integrated circuit which is driven with a low power while having a structure wherein a cell area can be reduced and methods for manufacturing the same.
2. Description of the Prior Art
In recent years, a remarkable spread of information processing equipment such as computers has been increasing demand for semiconductor memory devices. In particular, semiconductor memory devices having a large storage capacity and operable at a high speed are in great demand, which demand is followed by technological development to improve integration density, response and reliability of semiconductor memory devices.
Among semiconductor memory devices, a DRAM (Dynamic Random Access Memory) is well known as a memory which enables randon input and output of storage information. A DRAM generally comprises a memory cell array portion serving as a storage region wherein a great deal of storage information is stored and a peripheral circuit portion for inputting/outputting external signals.
The memory cells each array portion includes a memory cell comprising one transistor and one capacitor, and a bit line for transferring electric charges stored in the capacitor of the memory cell.
The peripheral circuit portion includes a Vcc power supply portion and a column decoder.
For writing to a conventional DRAM having such an arrangement, a column decoder in the peripheral circuit portion or the like first designates a memory cell. Then, signal charges are transmitted through the bit line to the designated memory cell. The signal charges transmitted through bit line are transmitted to a storage node of the capacitor by applying predetermined charges to a gate electrode. The signal charges transmitted to the storage node are stored in the capacitor. In a reading operation, signal charges are transmitted onto the bit line by applying a predetermined voltage to the gate electrode. The signal charges transmitted onto the bit line are externally read out through the column decoder.
Recently, in a semiconductor memory device, it is required that an area of each portion in the semiconductor memory device is made small in accordance with increasing of the capacity of a bit line. It is useful for decreasing the occupancy area of each portion in the semiconductor memory device to minutely form a configuration of the semiconductor memory device, and to provide efficient interconnections.
FIG. 1 is a plan view of a first example of a semiconductor device incorporating a contact structure according to a first conventional method, and FIG. 2 is a sectional view taken along II-II' in FIG. 1. As shown in FIG. 1, word lines 2 are formed spaced apart at a determined distance on a semiconductor substrate (not shown), and in a row pattern. Bit lines 8 are formed perpendicular to word lines 2 and parallel to one another. Field oxide films 1 are located between the bit lines 8 and word lines 2.
Referring now to FIG. 2, a conventional method of forming a semiconductor device is described below. First, predetermined portions of a semiconductor substrate 100 is field-oxidized to form field oxide films 1. Portions on the semiconductor substrate 100 which are not formed with the field oxide films 1 serve as active regions 200. A gate oxide film 10A then, is formed on the entire surface of the semiconductor substrate 100 typically by a thermal oxidation technique, covering the exposed area of the semiconductor substrate 100. A polysilicon layer is then conformally deposited over entire surface of the resultant semiconductor structure. The polysilicon layer thus formed on the semiconductor substrate 100 is patterned and etched to form the word lines 2 on the gate oxide film 10A. Thereafter, an oxide film is formed on the entire surface of the resultant structure typically by chemical vapor deposition(CVD) technique and is etched with for example, a reactive ion eating (RIE) technique thereby to form spacer 10B. Hereinafter, the gate oxide film 10A and the spacer 10B formed on both sides of the word line 2 are called the word line 2.
In order to form self-aligned a source region 3 and a drain region 4 of each transistor, the word lines 2 are then used as a mask for injecting dopant such a phosphorus into the semiconductor substrate 100. At this step, as shown in this figure, an impurity region located between word lines 2 is used as a drain region 4, and two transistors share one drain region 4. Then, a first insulating film 5 is deposited to a predetermined thickness on the semiconductor substrate 100 on which the transistors are formed. The first insulating film 5 is etched away so as to expose the source region 3. Then, on the exposed source region 3, a capacitor 7 for storing information charge of the memory device is formed. At this time, a contact region of the source region 3 and the capacitor 7 is called a storage node contact region 3A. Thereafter, a second insulating film 6 is deposited to a predetermined thickness on the entire surface of the semiconductor substrate 100 on which the capacitor 7 is formed. A portion of the second insulating film 6 is etched away so as to expose the drain region 4. A bit line 8 is formed so as to be in contact with the exposed drain region 4 to form a bit line contact 4A.
FIG. 3 is a cross-sectional view taken along line III-III' in FIG. 2 and shows the shape of an active region of the integrated circuit memory.
As shown in FIG. 3, an active region 200 is formed on a semiconductor substrate (not shown) so as to be a 90 degree rotated-I shape i.e., not upright with respect to the figure. For reducing a unit cell area of a transistor, two transistors are formed in one active region 200. That is, two word lines 2 are formed so as to pass one active region 200. A source (not shown in FIG. 3) and a drain (not shown in FIG. 3) are formed in the active region 200 on respective sides of the word line 2, as shown in FIG. 2. Further, a capacitor (not shown in FIG. 3) for storing a charge is in contact with the source, thereby forming the storage node contact region 3A. The drain is in contact with a bit line (not shown in FIG. 3), thereby forming the bit line contact region 4A.
As described above, the conventional memory integrated circuit having the active region of the 90 degree rotated-I shape has a pair of transistors, the pair of transistors share one drain in one active region. For this reason, in order to drive two transistors formed in one active region, at least a voltage of 1/2 Vcc is necessary. Therefore, it is difficult to satisfy the recent tendency requiring low power.
Further, in the view of the above method for manufacturing the memory integrated circuit, since the capacitor is formed before forming the bit line, the step-coverage caused due to the capacitor is adversely affected. Step coverage is a known measure of how well a film maintains its nominal thickness as it crosses over high and steep steps and is expressed by the ratio of the minimum thickness of a film as it crosses a step to the nominal thickness of the film on horizontal regions. Due to this, when forming the bit line, the contact of the bit line and the drain is not formed easily, thereby causing a poor interconnection. In addition, it is difficult to enlarge the area of the capacitor.
In order to overcome such problems, as another conventional embodiment, there is suggested a method where a capacitor is formed after a bit line is formed.
As shown in FIG. 4, an active region 200 is formed in a semiconductor substrate (not shown) by known field oxidation methods. Word lines 2 are formed parallel to each other on active region 200 and a field oxide film 1, being spaced apart by a predetermined distance. Bit lines 8 are formed parallel to each other on active region 200 and a field oxide film 1, each being spaced apart by a predetermined distance so as to be perpendicular to each of the word lines 2.
FIG. 5 is a cross-sectional view taken along line V-V' of FIG. 4.
As shown in FIG. 5, an active region 200 is defined in a semiconductor substrate 100 by a conventional field oxidation technique. A Word line 2 is formed on a predetermined portion of the semiconductor substrate 100 by the known technique. An impurity ion is implanted into the active region 200 exposed by a field oxide film 1 and the word line 2, thereby forming a source region 3, and a drain region 4. A first insulating film 5 is deposited on the semiconductor substrate 100 on which a transistor is formed. The first insulating film 5 is etched to expose the drain region 4 of the transistor. A bit line 8 is formed so as to be in contact with the exposed drain region 4. At this time, a portion where the drain region 4 and the bit line 8 are in contact with each other is called a bit line contact region 4A. Then, a second insulating film 6 is deposited on entire surface of the semiconductor substrate 100 on which the bit line 8 is formed. Predetermined portions of the second insulating film 6 and the first insulating film 5 are in turn etched to expose source region 3. A capacitor 7 for storing information is formed on the source region 3. At that time, a portion where source region 3 and the capacitor 7 are in contact with each other is called a storage node contact region 3A.
FIG. 6 is a cross-sectional view taken along line VI-VI' of FIG. 5, and shows the shape of the active region of the memory integrated circuit.
With the conventional 90 degree rotated-I shape, it is difficult to form the bit line before forming of the capacitor. Therefore, the active region 200 of an reverse-T shape is formed. The word lines 2 are formed so as to pass two by two the respective active regions 200. In the active region 200 of reverse-T shape, two sources (not shown) are formed on respective sides of the word lines 2 of the direction of X-axis (left to right with respect to Figure), and a drain (not shown) is formed between the word line 2 in the direction of Y-axis (up and down with respect to the Figure).
The source is in contact with a capacitor (not shown), and this portion is called a storage node contact region 3A. The drain is in contact with a bit line (not shown), and this portion is called a bit line contact region 4A.
According to the last described method for manufacturing the memory integrated circuit, the memory integrated circuit having the reverse-T shape active region forms the bit line and the capacitor by changing the manufacturing steps thereof, thereby improving the step-coverage. However, from a structural view, two transistors are formed on one active region as usual. Thus, it is difficult to drive the transistor by a low power. Further, the area of the active region is increased by the leg portion of the reverse-T shape, thus the area of the cell is increased to about 33%.